User Tools

Site Tools


doc:hardware:cpu

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision
Previous revision
doc:hardware:cpu [2013/11/03 21:33]
lorema
doc:hardware:cpu [2016/05/13 00:13] (current)
RAThomas [The ISA (Instruction set architecture)] clean up the patent confusion
Line 1: Line 1:
 +====== The CPU aka the Core ======
  
 +===== CPU classification =====
 +When looking at the usual [[wp>​Central processing unit]] a couple of things come into mind:
 +  - its **[[wp>​Instruction set]]** (jump directly to a [[wp>​List of instruction sets]]) and then see **[[https://​dev.openwrt.org/​browser/​trunk/​target/​Config.in|OpenWrt Buildroot - Supported ARCHes]]**
 +  - **[[wp>​Template:​Multimedia extensions|Extensions]]** to the Instruction Set, e.g. [[wp>MMX (instruction set)|MMX]] or [[wp>​Advanced Vector Extensions|AVX]] or [[wp>​AES-NI]])
 +  - and its [[wp>CPU design|design]] manifesting into a concrete **[[wp>​Microarchitecture]]** (e.g. [[wp>​Intel Core (microarchitecture)|Core2]] or [[wp>​NetBurst (microarchitecture)|NetBurst]] or [[wp>​AMD_K5]])
 +  - concrete CPUs designed conforming to the same microarchitecture further differentiate from one another in the Frequency and Cache sizes
 +
 +Examples:
 +  * x86 is one distinct ISA and the i386SX was one distinct microarchitecture,​ and the i486DX2 another one, and the Cyrix 
 +  * ARMv5 is one distinct ISA and the ARM926EJ-S is one distinct microarchitecture based upon it
 +  * MIPS32 is one distinct ISA and the MIPS 24K, 34K or the 74K are all based upon it.
 +
 +You could also look at the type of Processor:
 +  * common processor with [[wp>​Arithmetic logic unit]] [[wp>​Memory management unit]] and [[wp>​Floating-point unit]].
 +  * [[wp>​Digital signal processor]]
 +  * what once was a distinct chip [[wp>​Graphics processing unit]] is now merely an [[http://​pics.computerbase.de/​3/​7/​8/​1/​8/​1_m.jpg|SIMD Engine Array]]
 +
 +===== Semiconductor companies =====
 +  * There are fabless companies who do only CPU design (e.g. [[wp>ARM Holdings]], [[wp>​Imagination Technologies]],​ [[wp>​Nvidia]], ​ and [[wp>​Advanced Micro Devices]])
 +  * and there are companies who own and operate Chip foundries (e.g. [[wp>​Taiwan Semiconductor Manufacturing Company]], [[wp>​GlobalFoundries]],​ [[wp>​Samsung]],​ etc.).
 +  * And then there is the [[wp>​Intel Corporation]],​ who still does both.
 +
 +
 +===== CPU purchase =====
 +When you want to purchase a CPU (or a couple of thousand) you have three choices:
 +  * buy hardware, a Chip, which is a [[wp>Die (integrated circuit)]] on a/bonded to a [[wp>​Chip carrier]]
 +  * buy Hard IP
 +  * buy Soft IP
 +
 +
 +To understand the difference between Hard IP and Soft IP you have to get a grasp of the processes of designing and of manufacturing of IC.
 +
 +===== Explanation =====
 +==== The ISA (Instruction set architecture) ====
 +
 +Without going into detail you could say, the ISA is the whole of commands (absolute instructions/​machine code instruction) the programmer/​compiler can see and use. If you program in assembler (or write machine code), you will have to know these instructions. If you program in a higher language, the compiler (or the cross-compiler) will take care of this for you. It will translate your source code into machine code for the ISA (in compiler surroundings abbreviated ARCH for architecture) specified.
 +
 +When you "cross compile"​ it means that you compile the source code on a machine that has a different ISA than that of the target machine you will run the compiled code on. For this the compiler needs to know the ISA for your target ARCH (architecture). Follow this link to learn how to [[doc:​devel:​crosscompile| cross compile]]. For more information on ISA, see the white paper at: [[wp>​Instruction_set_architecture|Instruction set]].
 +
 +Designing an Instruction Set is more just saying "I want to use these instructions"​. The underlying logic of how data goes in/out and how it is manipulated when instructions are processed, this has to be designed as well.  How all of this can be implemented in a physical [[wp>​Integrated Circuit]] (IC or simply Chip) has to be designed too. Some stages of this overall design are often covered by patents or other Intellectual Property protections. Some CPU design companies exist only to create and license their designs to others who will integrate them into their own physical devices.
 +
 +  * see [[wp>​Calling convention]]
 +  * see [[wp>​Opcode]]
 +
 +
 +=== Example: MIPS ===
 +You can find a distinct Wiki for GNU/Linux and the MIPS instruction set here:  [[http://​www.linux-mips.org/​wiki/​Main_Page]].
 +
 +MIPS (Microprocessor without Interlocked Pipeline Stages) is a instruction set architecture (ISA) developed by MIPS Computer Systems. Multiple revisions of the MIPS instruction set exist the only current ones being MIPS32 and MIPS64. As there are //​extensions//​ to the x86 ISA, like MMX, SSE, 3DNow!, etc, there are some available for MIPS as well. MIPS Technologies calls them ASE (Application-specific extensions). Read about them here: [[http://​www.mips.com/​products/​architectures/​]].
 +
 +{{ http://​www.embeddeddeveloper.com/​cores/​images/​Cores_FChart08.jpg}}
 +^               ​^ ​ MIPS Classic Processors ​                                                 ^^^^^^^^^^^ ​ MIPS Aptiv Processors ​ ^^^ MIPS Warrior ^^^
 +^               ^ 4KSd ^ M4K ^ M14K ^ 4KE ^ M14Kc ^ 24K ^ 24KE ^ 34K ^ 74K ^ 1004K ^ 1074K ^ microAptiv ^ interAptiv ^ proAptiv ^ Warrior-M ^ Warrior-I ^ Warrior-P ^
 +|  MIPS32 ​        ​| ​ ✔  |  ✔  |  ✔  |  ✔  |  ✔  |  ✔  |  ✔  |  ✔  |  ✔  |  ✔  |    |    |    |    |    |    |    |
 +|  MIPS64 ​        ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​   |    |    |    |    |    |    |
 +|  MIPS16e ​       |  O  |  O  |     ​| ​ O  |     ​| ​ ✔  |  ✔  |  ✔  |  ✔  |  ✔  |    |    |    |    |    |    |    |
 +|  MIPS DSP ASE   ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​ ✔  |  ✔  |  ✔  |  ✔  |    |    |    |    |    |    |    |
 +|  MIPS MT ASE    |     ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​ ✔  |     ​| ​ ✔  |    |    |    |    |    |    |    |
 +|  SmartMIPS ASE  |  ✔  |     ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​   |    |    |    |    |    |    |
 +|  microMIPS ​     |     ​| ​    ​| ​ ✔  |     ​| ​ ✔  |     ​| ​    ​| ​    ​| ​    ​| ​    ​| ​   |    |    |    |    |    |    |
 +|  MIPS-3D ASE    |     ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​    ​| ​   |    |    |    |    |    |    |
 +
 +  * AFAIK all MIPS classic processors are [[wp>​Out-of-order execution|in-order execution]] CPUs because the developers claimed, that the silicon surface and power consumption of the OUT-OF-ORDER logic would outweigh the processing power benefit. Instead they experimented with Multi-Threading and such to achieve a similar processing power increase but with less silicon.
 +  * The newer MIPS Aptiv Processors are reported to be all [[wp>​Out-of-order execution|Out-of-order]] CPUs.
 +  * Please do note, that there are a couple of MIPS32 and/or MIPS64 instruction set licensees, e.g. Broadcom, who design their own CPU Architectures based on the MIPS Instruction sets. Cf. [[doc:​hardware:​soc#​companies]] for some overview.
 +  *Dunno about Linux support for this stuff here: [[http://​www.imgtec.com/​ensigma/​ensigma-technology.asp]]
 +
 +
 +
 +To understand the concrete differences between the different CPU designs, you will have to go [[http://​www.mips.com/​products/​cores/​]]. This should only give you an overview to get a better grasp of the embedded world. And please understand, that //24KE// is not necessarily a CPU you can buy, or even a CPU contained on the SoC. It the a plan to manufacture the IC of a CPU! A contractor can realize this 1:1 into IC but does not have to.
 +
 +To understand a bit better, how this is embedded on the SoC, see [[http://​www.mips.com/​products/​platforms/​]].
 +
 +=== Example: ARM ===
 +The abbreviation stands for Advanced RISC Machine aka Acorn RISC Machine. ARM Holdings.
 +
 +For some reasons, the companies does not want to compete with each other, so on the router/wifi market MIPS cores are predominant. On the smart phone market it is the other way around, and we have ARM exclusively. However there is at least one neat device on which OpenWrt is running, so we will include this:
 +
 +
 +^  ISA ^  ISA+Extensions ​ ^  CPU  ^  Features ​ ^  Cache (I/D), MMU  ^  Devices ​ ^  Products ​ ^
 +|ARMv5|ARMv5 TEJ | ARM926EJ-S | Thumb, Jazelle DBX, Enhanced DSP instructions | variable, TCMs, MMU| Texas Instruments OMAP1710, OMAP1610, OMAP1611, OMAP1612, OMAP-L137, OMAP-L138; Qualcomm MSM6100, MSM6125, MSM6225, MSM6245, MSM6250, MSM6255A, MSM6260, MSM6275, MSM6280, MSM6300, MSM6500, MSM6800; Freescale i.MX21, i.MX27, Atmel AT91SAM9, NXP Semiconductors,​ Samsung S3C2412 LPC30xx, NEC C10046F5-211-PN2-A SoC – undocumented core in the ATi Hollywood graphics chip used in the Wii,[25] Telechips TCC7801, TCC7901, ZiiLABS ZMS-05, Rockchip RK2806 and RK2808, NeoMagic MiMagic Family MM6, MM6+, MM8, MTV. | Mobile phones: Sony Ericsson (K, W series); Siemens and Benq (x65 series and newer); LG Arena; , GPH Wiz, Squeezebox Duet Controller (Samsung S3C2412). Squeezebox Radio; Buffalo TeraStation Live (NAS); Drobo FS (NAS); Western Digital MyBook I World Edition; Western Digital MyBook II World Edition; Seagate FreeAgent DockStar STDSD10G-RK;​ Seagate FreeAgent GoFlex Home; Chumby Classic |
 +
 +To understand the concrete differences between the different versions, you will have to go somewhere else. This should only give you an overview to get a better grasp of the embedded world. And please understand, that //​ARM926EJ-S//​ is not necessarily a CPU you can buy, or even a CPU contained on the SoC. It is only the model of a CPU! A contractor can realize this 1:1 into IC but does not have to. For example the manufacturer Marvell make the //Marvell Feroceon CPU//, which is based on the Design of the //​ARM926EJ-S//​ (sometimes it includes CESA). //Marvell Kirkwood// is the denomination of a family of SoCs, not of a CPU design.
 +
 +  * [[http://​www.arm.com/​markets/​enterprise/​home-networking.php]] about SoC
 +  * [[wp>​Template:​ARM-based_chips|CPUs based on ARM Instruction set]]
 +
 +On [[http://​hackipedia.org/​Hardware/​CPU/​]],​ for example, there are some txt-documents about the ARM-architecture.
 +
 +
 +=== Example: Other ===
 +[[wp>​x86]],​ [[wp>​Ubicom32]],​ [[wp>DEC Alpha]], [[wp>​PowerPC]],​ [[wp>​Intel Itanium architecture]],​ [[wp>​SuperH]],​ etc.
 +
 +=== Extensions ===
 +Code compiled for ARM should run on any ARM-ISA, but code speficifally compiled for ARMv7 will not run smoothly or not at all on an ARMv5 ISA. So, it is imperative to keep the ISA stable for many years, thus there are only few or no updates at all! To still be able to develop and advance the ISA, and thus give the programmer (or the compiler) more options to do theirs stuff, manufactures (or better developers) extend ISAs with so called extensions. See [[wp>​Template:​Multimedia_extensions]].
 +
 +**NOTE:** In the FOSS-"​World",​ this isn't such a big issue, since we have the Source-Code and with an updated compiler we can recompile the code as we like and obtain binaries that work an any architecture. And actually we do exactly that at OpenWrt. When you choose the option [[doc:​howto:​build]] you do download the very latest source code for the cross compiler and cross compile the source code with that!
 +
 +
 +==== The Microarchitecture ====
 +While the ISA is only the set of commands available, to use it, you need to create a CPU based on one. While an abstraction of the ISA is build in silicon, the CPU needs more functional units to be able to work and also to perform as well as possible. The denomination for this is not clear-cut, everyone names differently. Instead of //​microarchitecture//,​ sometimes this is referred to as //"​processor organization"//​ or //"​processor design"//​ or //"​processor implementation"//​. It deals with the organization of the different functional units of the CPU. For the same ISA, you could develop a whole lot of microarchitectures. A hopefully good example is the intel i486 and the intel Pentium Pro (it's the immediate predecessor the Pentium II, whereas the Pentium is not). Both CPU have (almost) the same ISA, but very different MAs.
 +
 +  * CPU components (functional units): [[wp>​microcode|Microcode]] [[wp>​Arithmetic logic unit|Arithmetic logic unit (ALU)]] [[wp>​Address generation unit|Address generation unit (AGU)]] [[wp>​Barrel shifter]] [[wp>​Floating-point unit|Floating-point unit (FPU)]] [[wp>​Back-side bus]] [[wp>​Multiplexer]] [[wp>​Demultiplexer]] [[wp>​Processor register|Registers]] [[wp>​Memory management unit|Memory management unit (MMU)]] [[wp>​Translation lookaside buffer|Translation lookaside buffer (TLB)]] [[wp>CPU cache|Cache]] [[wp>​register file|Register file]][[wp>​control unit|Control unit]] [[wp>​clock rate|Clock rate]]
 +  * see [[wp>CPU design]] to learn about the tasks CPU design focuses on
 +  * see [[wp>​Microarchitecture]] to learn about some micro-architectural concepts with the help of some schematic examples from the x86 
 +
 +
 +===== IP core =====
 +IP core means "​Intellectual Property Core". It a piece of software that can be licensed from companies such as MIPS or ARM. It's a chip layout design and consists of of schematics and descriptions to manufacture ICs with the functionality of a CPU. With this, the licensee can go to an semiconductor foundry and commission the manufacturing of Chips with the functionality of merely the CPU purchased. But usually, the designs of the CPU are combined with the designs of other ICs serving other tasks. Then the licensee commissions the manufacture of Chips, which do have the functionality of a complete [[doc:​hardware:​SoC]],​ and not merely that of a CPU.
 +
 +Often different types can be licensed, a //soft IP core// or //hard IP core//. To understand the difference between them you need to understand even more of the chip design process. Maybe the article [[doc:​hardware:​ic]] helps a little with that.
 +
 +Also, exceptionally there a good article about this in the wikipedia: [[http://​en.wikipedia.org/​wiki/​Semiconductor_intellectual_property_core|IP core]].
 +
 +===== The SoC =====
 +-> [[doc:​hardware:​soc|SoC]] What do licensees include in a SoC?
 +
 +===== The Device =====
 +-> [[toh:​start]]
 +
 +A Manufacturer of "​devices"/​routers/​access points buys SoCs, RAM-Chips, Flash-Chips,​ etc. from the manufacturers of these and solder them onto a circuit board. Then they put the whole thing into a body housing, write 
 +
 +documentation for the end customer and sell them whole sale.
 +
 +For a List of Devices and Manufacturers,​ simply have look at the [[:​toh:​start|Table of Hardware]].
 +
 +===== Manufacturing =====
 +-> [[doc:​hardware:​ic|Integrated Circuit]] whether [[wp>​Central processing unit|CPU]], [[wp>​Graphics processing unit|GPU]], [[wp>​Dynamic random-access memory|DRAM]],​ [[wp>​Static random-access memory|SRAM]],​ [[wp>​Digital signal processor|DPS]],​ [[wp>​Floating-point unit|FPU]] etc. all are realized as ICs.
 +
 +
 +==== Wikipedia Articles ====
 +
 +  * [[wp>​Integrated_circuit#​Manufacturing]] <- mediocre article
 +  * [[wp>​Semiconductor device fabrication]] <- miserable article, please replace with something better
 +
 +  * [[wp>​Application binary interface]]