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doc:hardware:cpu [2013/11/03 21:33]
lorema
doc:hardware:cpu [2014/05/14 08:57] (current)
lorema
Line 4: Line 4:
 When looking at the usual [[wp>​Central processing unit]] a couple of things come into mind: When looking at the usual [[wp>​Central processing unit]] a couple of things come into mind:
   - its **[[wp>​Instruction set]]** (jump directly to a [[wp>​List of instruction sets]]) and then see **[[https://​dev.openwrt.org/​browser/​trunk/​target/​Config.in|OpenWrt Buildroot - Supported ARCHes]]**   - its **[[wp>​Instruction set]]** (jump directly to a [[wp>​List of instruction sets]]) and then see **[[https://​dev.openwrt.org/​browser/​trunk/​target/​Config.in|OpenWrt Buildroot - Supported ARCHes]]**
-  - and its [[wp>CPU design|design]] manifesting into a concrete **[[wp>​Microarchitecture]]** (e.g. [[wp>​Intel Core (microarchitecture)|Core2]] or [[wp>​NetBurst (microarchitecture)|NetBurst]] or [[wp>​AMD_K5]]) 
   - **[[wp>​Template:​Multimedia extensions|Extensions]]** to the Instruction Set, e.g. [[wp>MMX (instruction set)|MMX]] or [[wp>​Advanced Vector Extensions|AVX]] or [[wp>​AES-NI]])   - **[[wp>​Template:​Multimedia extensions|Extensions]]** to the Instruction Set, e.g. [[wp>MMX (instruction set)|MMX]] or [[wp>​Advanced Vector Extensions|AVX]] or [[wp>​AES-NI]])
 +  - and its [[wp>CPU design|design]] manifesting into a concrete **[[wp>​Microarchitecture]]** (e.g. [[wp>​Intel Core (microarchitecture)|Core2]] or [[wp>​NetBurst (microarchitecture)|NetBurst]] or [[wp>​AMD_K5]])
 +  - concrete CPUs designed conforming to the same microarchitecture further differentiate from one another in the Frequency and Cache sizes
  
 Examples: Examples:
doc/hardware/cpu.1383510814.txt.bz2 · Last modified: 2013/11/03 21:33 by lorema