Marvell Technology Group SoCs
Marvell designed CPUs
Marvell holds a full architecture license for the ARM instruction set, allowing it to design CPUs to implement the ARM instruction set, and not to just license a processor core designed by ARM holdings. E.g.
Marvell Feroceon has a variable-length processing pipeline that allows out-of-order instruction execution. The Feroceon made some significant changes to the standard ARM fixed pipeline, with a variable-stage pipeline that ranges from six stages to eight if the writeback stage is included.
Most ARM processors (and many other embedded processors) employ an in-order, fixed-stage pipeline design because it is simpler to construct and uses less logic. The instructions per cycle (IPC) of an in-order, fixed-stage pipeline will often be fairly low unless other features are added, such as multithreading or superscalarity.
In contrast, a variable-stage pipeline optimizes the number of clock cycles needed from issue to retire on each instruction, avoids wasting processor resources, and minimizes the branch penalty from dead clock cycles. With these changes to the ARM core, the Feroceon processor could also support dual-issue operation.
Marvell Sheeva 88SV131 = Marvell designed ARMv5TE-compliant
Marvell Flareon PJ4 = Marvell designed armv7-a-compliant?
See also marvell.cesa
There seem to be some confusion regarding the Names "Sheeva" and "Feroceon". One pdfs states: "The Marvell® 88F6192 SoC with SheevaTM embedded CPU technology, is a high-performance integrated controller for value class applications. It integrates the Marvell Sheeva CPU core which is fully ARMv5TE-compliant with a 256KB L2 Cache. The 88F6192 builds upon Marvell’s innovative Feroceon® family of processors.
Oh, also read: http://lists.infradead.org/pipermail/linux-arm-kernel/2012-July/109891.html
Boards based on the Marvell MV88 F5 18x / MV88 F5 28x SoCs .
Boards based on the Marvell MV88 F6 1xx / MV88 F6 2xx SoCs.